Design For Test or DFT is a design philosophy that takes into
account test methods and testability hooks at the beginning of the card
design cycle.
Starting a design cycle by implementing one or methods to insure the card
may be completely tested shortens the board test and debug phase, although
it also increases the design phase but to a lesser degree.
Design For Testability may include adding any number of features into the
Circuit Card Assembly [CCA] to promote ease of testing.
Adding test pads so the CCA could be tested for shorts and open traces
using either a clam shell, Bed-of-Nails, or flying probe provides an
opportunity for DC continuity of the bare board.
Including ICs which incorporate JTAG interfaces insures that
point-to-point inter-connects between ICs, or shorted or lifted IC pads
will be detected. Refer below for JTAG information.
Adding scope probe points, and grounding pins is another form of Design For Testability.
Introducing IC gates or functions that may be switched in or out to enhance debug is yet another form of Design For Testability.
IEEE Std 1149.1-1990 JTAG (Joint Test Action Group); Test Access
Port and Boundary-Scan Architecture. This is a serial bus with four
signals: Test Clock (TCK), Test Mode Select (TMS), Test
Data Input (TDI), and Test Data Output (TDO). The bus is used
as a test bus for the 'Boundary-Scan' of ICs, as in
Design-For-Testability (DFT). To use JTAG, during the design, you most
select JTAG compatible devices. ICs supporting JTAG will have the four
additional pins listed above. Devices reside on the bus in a daisy chain,
with TDO of one device feeding TDI of the next device. In addition to
having the pins listed above each device most have a Boundary-Scan
Register. The Boundary-Scan Register may be used to test the
interconnection between ICs [Chip-to-Chip] or test with in the IC.
Boundary-scan tests can be used to check continuity between devices.
Continuity checks on PWB nets may be performed by sending out a know
pattern and receiving that same pattern at the input to another IC(s).
Not receiving the test signal or pattern would indicate a broken PWB
trace, a failed IC, or cold solder joint.
The complete JTAG interface description and pinout is listed on the
JTAG Interface page.
Engineering Design Key words: Design For Test, DFT, JTAG Bus, IEEE-std-1149.1, Boundary Scan, JTAG, Scan, Bscan, Boundary Scan, BST, Board-Under-Test, Testability, Joint Test Action Group, Integrated Circuit, IC Bus, Chip-to-Chip, Electrical layer, Multi-Drop, Standard, Serial Communications interface, Interface Standard Data Bus, Standard, Specification, Spec, Validate, IC, Physical Interface, Description, Fault isolation.
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