VXI Bus Description and VXI device Manufacturers

VXI Bus

VME {Versa Module Europa} Extension for Instrumentation
VXI-1

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VXI Bus Description

VXIbus System

VXI Bus Description {Brief} ---- Electromechanical super set and logical subset of the VME spec ---- The VXI spec determines chassis and Card requirements not defined in the VME spec. Also additional card sizes; 'D' which I do not think is defined in VME. Upgrades to VME are carried; I believe the new 5-row connector spec is handled. Card-to-Card spacing is changed from 0.8 to 1.2. Many of these changes are detailed on this page. In addition, many card requirements are levied with VXI; Heat dissipation, and EMI radiation to name a few. Differences between VXI and VME {VXI P2 additions} CLK10 > 10MHz differential ECL Clock; Sourced from Slot 0 bused to slots 1 to 12 on P2. Buffering occurs on the back plane, with each slot appearing as a single destination (individually buffered). TTLTRG0-7* > TTL Trigger Lines; Open Collector TTL lines used for intermodule communication. Any module may drive or receive these lines. ECLTRG0-1 > ECL single ended 50 ohm Trigger Lines; Any module may drive or receive these lines. Used for intermodule timing. LBUS00-11 > Local Bus, Daisy chained keyed bus; may be either ECL or TTL. Bused between adjacent slot only, The keyed position determines if two adjacent cards will talk to one another, and prevents incompatible boards from being installed. Differences between VXI and VME {VXI P3 additions} Many of these additions; Power Ground, ect. can be found further down the page. CLK100 > 100MHz differential ECL Clock; Sourced from Slot 0 bused to slots 1 to 12 on P3. Buffering occurs on the back plane, with each slot appearing as a single destination (individually buffered). SYNC100> Bused to slots 1 to 12 on P3. Buffering occurs on the back plane, with each slot appearing as a single destination (individually buffered). ECLTRG2-5 > ECL single ended 50 ohm Trigger Lines; Any module may drive or receive these lines. Used for intermodule timing. Identical to lines 0 and 1 on the P2 bus. LBUS12-35 > Local Bus, Daisy chained keyed bus; may be either ECL or TTL. Bused between adjacent slot only, I believe the keyed position determines if two adjacent cards will talk to one another. Identical to P@ Local Bus Lines The VME bus is a scalable backplane bus interface. Cards may be produced which respond to the following Address widths or Data widths: A01 - A15 A01 - A23 A01 - A31 D00 - D07 D00 - D15 D00 - D23 D00 - D31 D00 - D63 The tables below detail the required control signals to produce the different bus widths Three main types of cards reside on the bus. The Controller, which supervises bus activity. A Master which Reads/Writes data to a Slave board, and a Slave interface which simply allows data to be accessed via a Read or Write from a Master. Controller The Controller 'controls' access to the bus. Upon receiving a "Bus Request" signal from a bus Master, the Controller will "Bus Grant" that Master access to the bus. The Controller also handles Interrupts on the bus. When an Interrupt is received on one of the IRQ lines the Controller will process that Interrupt by accessing the Interrupting card, and acknowledge the Interrupt. Only one Controller may reside on the VME bus. Master The bus Master Reads and Writes data to or from a Slave board. The Master " Bus Requests" access to the VME bus from the Controller. Once the Controller " Bus Grants" the Master access, the Master drives the Address and Data bus to perform a data transfer to a Slave board. Any number of bus Masters may reside on the VME bus, but only one may have control of the bus at any one time. Slave A Slave interface simply monitors the Address and Data bus for Reads or Writes sent to it. Once a correctly decoded address is received the Slave will either receive information {for a Write}, or output information onto the Data bus in the case of a Read. The bus Master continues to control the Data bus during either interface. A Slave may also generate Interrupts over any of 7 IRQ lines. The Interrupts are acknowledged by the bus Controller. Any number of Slave boards may reside on the VME bus L. Davis @ 2/3/2000

Extracted from -- Interface Board Design Document 1/03/93, Larry Davis
VME Bus Address Path Width

Extracted from -- Interface Board Design Document 1/03/93, Larry Davis

Up_grades
The original VME spec was IEEE 1014-1987 which defined two 3 row P1/P2 connectors, providing 32 bit Data Xfers @ 40MBytes/second. Revision C allowed 64 bit Data transfers, with the upper 32 data bits being multiplexed onto the address bus (after the address was broadcast). ANSI/VITA 1-1994 termed VME64, added a 5 Row P1/P2 connector, and many other features providing transfers of @ 80MBytes/second. VITA 1.1-1997, termed VME64x defined the 'z' and 'd' rows of P1 and added the P0 connector. VME320 increased the bus speed to 320 Mbytes/sec on the back-plane.

There are a number of other specification which increase the data through-put even higher by using the "user defined" P2 pins, the P0 connector or by bringing the data out the front panel. ANSI/VITA 10-1995 Termed SKYchannel uses the P2 to transfer data @ 320 Mbytes/sec. P₂CI also uses the user defined P2 pins. ANSI/VITA 17 Termed FPDP (Front Panel Data Port) uses an 32-bit synchronous data bus to transfer data at 160MBytes/sec, using differential PECL over the front panel. ANSI/VITA 5-1994 or Raceway Interlink uses a P2 Backplane daughter card. There are a number of others. Refer to P2 Add-On Buses on the web for additional buses.

The original VME specification allowed for a 32 bit address bus and a data bus, which produced a maximum transfer rate of 40 MBps. Revision C provided another 32 bits of data to be multiplexed onto the address bus, once the address cycle was complete, during block transfers. This 64 bit data bus increased the maximum transfer speed to 80MBps. Revision D increased the data bus to 64 bits, keeping the address width at 32 bits. The back-plane connectors were also changed to 5 rows from the original 3 rows, which allowed the addition of more ground pins.

There are two main types of Data transfers on the bus; single cycle, or Block Transfer. A single cycle consists of the Master performing an Address cycle followed by a single Data transfer cycle. A block transfer cycle consists of the Master performing a single Address cycle followed by up to 256 data cycles. A Block Transfer consists of up to a 256 Byte transfers. Block Transfers increase the though-put of the bus by reducing the over head. For 256 bytes only one bus request cycle is required, and only one Address cycle is required.

{VXI Bus Index}

VXI Interface Bus Pin Out

VXI P1 Connector Pin out
VXI P2 Pinout for Slot 0 and Slot 1-to-12
VXI P3 Pinout for Slot 0 and Slot 1-to-12

VXI Bus card dimensions [Form Factor]

Three card [PWB] heights are allowed 3U, 6U, or 9U; a single slot card is 6T wide. Length is either 160mm or 340mm
Height is given in 'U' [1U = 43.60mm], Length is given in 'mm', Width is given in 'T', or HP [1HP = 5.08mm [HP: Horizontal Pitch] ; Card sizes listed below are one slot or 6T wide
A size = 3U x 160mm, B size = 6U x 160mm, C size = 6U x 340mm, D size = 9U x 340mm ... H x L x W {@ width=6T}

'C' Size Board dimensions Detailed, Mechanical

'D' Size Board dimensions Detailed, Mechanical

3D {'A', 'B', 'C', 'D'} Board Dimensions [Sizes] General

Front Panel dimension Details C Size or D Size
Front Panel Mounting dimension Details C Size or D Size
Board Guide C Size or D Size * Drawings removed because of Bandwidth issues.

VXI Card Manufacturers

{VXI Bus Index}

VXI Interface IC Manufacturers

The VME bus uses normal TTL devices.
The VME64-ETL specification uses the ABTE (Advanced - BiCMOS - Technology - Enhanced Transceiver) Logic family.
VXI defines TTL signals, ECL signals and Analog signals up to 42 volts. Refer to the pinout tables to determine the signally interface levels.

Fairchild Semiconductor Corp. {VME320 8-Bit Registered Bus Transceiver IC Manufacturer}

IDT {VME64 Bus Controller-VME Bridges to PCI/Local Bus, PCI-X/VME Bridge [Tempe]}

Inicore Inc. {Slave Controller IP Cores}

Texas Instruments 'TI' {74VMEH22501, 8 bit transceiver/2eSST, also ABTE16245 ICs}

IC Manufacturers {All other types}

{VXI-Bus Index}

VXI Standards and Specifications Info

IEEE 1155-1992{VXI} IEEE Standard VMEbus Extensions for Instrumentation: VXIbus [Version 1.0, August 1987]
VXI Reversion 2.0 VXIbus System Specification, August 1998
VXI Reversion 3.0 VXIbus System Specification, January 2004

IEEE 1014-1987{VME} The original VME Spec. {3 row P1/P2, 32 bit Xfers, 64 w/ the address bus MUXed}
ANSI/VITA 1-1994 {VME64} added 5 Row P1/P2, P0...many other features
VITA 1.1-1997 {VME64x} which defined the 'z' and 'd' row of P1
IEEE 1101.1 Mechanical Specifications

{VXI Bus Index}

VXI Connector Manufacturers {603-2-IECC096xx-xxx}

The VXI standard defines module connectors as DIN 41612 Class II Style C [Type C]
P1 and P2 are 96 pin DIN (41612) 3 rows x 32 pins @ IEEE 1014-1987
Class II defines an endurance of 400 insertion/extraction cycles.

Connector types also found on the VME Bus:
P1 and P2 are 160 pin DIN (41612) 5 rows x 32 pins @ ANSI/VITA 1-1994
P0 95 pin 2mm 5 rows x 19 pins (IEC 1076-4-101), PCI style @ VITA 1.1-1997
P2 Split DIN / RF Coax @ - The number of Coax varies between ~ 2 and 8 RF connectors
Split Connector Types DIN + Coax @ 78 + 2, 60 + 4, 42 + 6, 24 + 8

VME DIN Connector Dimensions

AVX Corp. {DIN 41612 - many types}

ept {DIN 41612 Connectors}

Berg 'FCI' {VME DIN 4162/RF Connectors}

Erni {3x32 Row-DIN 41612-Split DIN/Coax 78 + 2 / 60 + 4 / 42 + 6 / 24 + 8-CPCI 2mm type}

Conec {DIN 41612/41617 Connector Manufacturer}

FCI {VME DIN 4162/RF Connectors}

Harting {DIN 41612 - 5 and 3 Row}

Hirose Electronic {DIN 3/5 Row-DIN 41612/IEC 603-2/DIN 41612M - High-frequency coaxial hybrid connector Manufacturer}

Molex {3x32 Row-DIN 41612-Split DIN/Coax 78 + 2 / 60 + 4 / 42 + 6 / 24 + 8 Styles}

Phoenix {DIN41612 Connectors-PKZ Styles}

Robinson Nugent "3M" {C-Form 3x32 Row DIN 41612-5x19 row 95 pin IESC 1076-4-101}

Tyco Electronics Corp. {3x32 Row-DIN 41612-Split DIN/Coax 78 + 2 / 60 + 4 / 42 + 6 / 24 + 8-CPCI 2mm type}

2mm connector manufacturers are listed on the cPCI Bus page

{VXI Bus Manufacturers Index}

VXI Chassis Manufacturer Requirements

A VXI Chassis will have between 1 and 13 slots. A 13 slot is the maximum board size.

Chassis Terminology:
"A-size" mainframe: Provides J1 only {mandatory}, allows for the insertion of an A-size module only.
"B-size" mainframe: Provides J1 {mandatory}, J2 {optional}, allows for the insertion of a B-size module.
"C-size" mainframe: Provides J1 {mandatory}, J2 {optional}, allows for the insertion of a C-size module.
"D-size" mainframe: Provides J1 {mandatory}, J2 and J3{optional}, allows for the insertion of a D-size module.

Additional VXI Chassis Requirements:
Card guides shall be made of non-conductive material, or be isolated from chassis ground.
Each backplane shall be a single monolithic board, within any slot position.
All mainframes shall provide chassis ground to the module front panels in the area of the front panel mounting screws.

Any voltage furnished by the mainframe power supply shall comply with the maximum Allowed Variation and maximum allowed DC Load Ripple/Noise.

**DC Voltage Specification**
Voltage	Description	Allowed Variation	DC Load Ripple/Noise	Induced Ripple/Noise	Purpose
+5V	+5V	+0.25V/-0.125V	50mV	50mV	Main Supply
+12V	+12V	+0.60V/-0.36V	50mV	50mV	Analog Devices
-12V	-12V	-0.60V/+0.36V	50mV	50mV	Analog Devices
+24V	+24V	+1.20V/-0.72V	150mV	150mV	Analog Devices
-24V	-24V	-1.20V/+0.72V	150mV	150mV	Analog Devices
-5.2V	-5.2V	-0.260V/+0.156V	50mV	50mV	ECL Devices
-2V	-2V	-0.10V/+0.10V	50mV	50mV	ECL Termination
+5V STDBY	+5 Vdc Standby	+0.25V/-0.125V	50mV	50mV	+5V Backup

VXI Chassis vendors

VXI 'C' Size Main Frame Drawing removed because of Bandwidth issues
VXI 'D' Size Main Frame * Same issue

{VXI Bus Manufacturers Index}

VXI System Software; No entries for software

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