VME (P2) Add on Buses

Versa Module Europa
IEEE 1014-1987

[SkyChannel Bus]
[RaceWay Bus] [Infiniband Bus] [P2CI Bus]
[FPDP Bus] [Autobahn Bus] [Myrinet Bus] [HIC Bus] [BusNet] [VXS Bus]
[VMEbus Pin-Out] [VME Bus Main Page]


Each of these [1990's] interfaces was an attempt to increase the speed of data transfers between VME boards.
Some might still be valid, while some will have faded from use long ago.
The problem with all of them is that a chassis would need to have at least two cards that used one of these standards to talk to each other.
Finding two VME cards that also had the same sub-interface was a task in itself.

SkyChannel Bus Description

ANSI/VITA 10-1995 {SKYchannel Packet Bus on VME P2} used to transfer data @ 320 Mbytes/sec between VME boards over SKYchannel Backplanes.
The SKYchannel Backplanes are really daughter cards which plug into the P2 connector on the VME backplane. The signals are TTL compatible.
The SKYchannel standard defines the Data Link Layer, and Physical Layer [electrical interface].
Each card of course needs to have a SKYchannel interface to communicate.

RACEWay Interlink Description

ANSI/VITA 5-1994 {RACEway Interlink} VME P2 Backplane Interconnect scheme
Defines the Protocol, Mechanical, and Electrical characteristics
The Raceway spec uses the user defined (row A and C) pins of the VME P2 connector. The additional rows added by VME64 (a and z) are not used.
The bus operates at 40MHz using 32 bit data transfers, possible transfer rate 480MBps. The bus operates on
adjacent slots on the VME bus as a Cross Bar Switch. Any number of slots may be interconnected, minimum is 4.

RaceWay products and Technical Literature may be found on Mercury Computer Systems.

{VME P2 Bus Index}

Infiniband Bus Description

Infiniband (High speed Serial Interconnect)
VITA 31 VME64 P0 Backplane Interconnect scheme. Up to 8 Infiniband connections are allowed per P0 connector.
Using a flat mating connector, with 3 grounds (outside/center pins) and 2 differential signal pairs.
Uses the Gigabit Ethernet connector / cable.
Refer to the InfiniBand Bus page for more information.

VITA 31 appears to be another standard which is no longer active, or never released.

P2CI Bus Description

VITA 27: {P2CI} PCI on P2 VME Compatible Interface. P2CI places the PCI Bus on the VME64 (5 row) P2 connector. The VME bus uses row B of the P2 connector, rows Z, A, C, and D are used for the P2CI bus. The bus speed remains the same for 33MHz; 132MBps [32 bit data], or 264MBps [64 bits data]. The P2CI standard does not reside on a 3U card because it uses the P2 [J2] connector. The P2CI interface may only reside on a 6U or 9U board. Refer to the PCI Bus page for a detailed PCI bus description. The electrical interface / IC drive levels will be the same as the PCI bus. All PCI interface ICs for the PCI bus are listed on then PCI Bus page. Note: the PCI Express Bus is set to replace the existing PCI bus implementation in the Personal Computer. PCI express is not compatible with the legacy PCI bus electrical standard. The PCI bus is single ended CMOS, while the PCI Express bus is differential LVDS.

This specification appears to have cancelled with out ever being released.
However a system design would still be free to add PCI onto any of the user defined pins.

{Back to VME P2 Bus Index}

FPDP Bus Description

ANSI/VITA 17 {FPDP; Front Panel Data Port} 32-bit synchronous front panel data bus @ 160MBytes/sec, differential PECL, over a 80 pin front panel connector.
The 1999 spec provides for a 1 meter ribbon cable. FPDP can be used to connect 2 separate VME chassis, or may be used with other bus types.
The point of the FPDP was to off-load board-to-board communication from the backplane and onto this interface.

Front Panel Data Port (FPDP), FPDP.com [which no longer exists, an indication that the interface is no longer in common usage].

---- {FiberXtreme} Serial FPDP approach, 105Mbps up to 10Km via a copper or fiber medium.
Serial FPDP operates at 1.0625GHz (Gbit Fibre Channel), or 2.48832GHz (SONET).
Serial FPDP will operate under a number of different connector/cable combinations; copper up to 30 meters, light up to 10 kilometers.

VITA 17 VMEbus Front Panel Signals
Pin Row A Row B Row C Row D
1 GND (1) STROB (2) GND (3) GND (4)
2 GND (5) GND (6) NRDY* (7) GND (8)
3 DIR* (9) GND (10) RESERVED (11) GND (12)
4 SUSPEND* (13) GND (14) GND (15) GND (16)
5 PIO2 (17) GND (18) PIO1 (19) GND (20)
6 RESERVED (21) GND (22) RESERVED (23) GND (24)
7 PSTROBE (25) GND (26) PSTROBE* (27) GND (28)
8 SYNC* (29) GND (30) DVALID* (31) GND (32)
9 D31 (33) D30 (34) GND (35) D29 (36)
10 D28 (37) GND (38) D27 (39) D26 (40)
11 GND (41) D25 (42) D24 (43) GND (44)
12 D23 (45) D22 (46) GND (47) D21 (48)
13 D20 (49) GND (50) D19 (51) D18 (52)
14 GND (53) D17 (54) D16 (55) GND (56)
15 D15 (57) D14 (58) GND (59) D13 (60)
16 D12 (61) GND (62) D11 (63) D10 (64)
17 GND (65) D09 (66) D08 (67) GND (68)
18 D07 (69) D06 (70) GND (71) D05 (72)
19 D04 (73) GND (74) D03 (75) D02 (76)
20 GND (77) D01 (78) D00 (79) GND (80)

The 80-pin flat cable connector uses 4 20-pin rows of pins on the board side.
The labeled pins represent the board side pin-out, while the numbers in the brackets correspond to the flat cable connector.
There is also an inverted pin-out [not shown] which switches the board side pinout but leaves the cable pin out unchanged.
The FPDP interface could run between two cards or daisy-chained between a number of cards.
There are two default locations for the front panel FPDP connectors, one at the top of the board and one near the bottom.
The top connector is 0.35 inches below the center line of the upper most P1 mounting screw.
The bottom connector is 0.35 inches above the center line of the bottom most P2 mounting screw.

{Back to VME P2 Bus Index}

Autobahn Description

Differential serial bus (2 lines) running at 200MBps using PECL logic (+3 and +4 volts) via half duplex, NRZ. Data is sent in blocks, each block is 4 bytes.
50 ohm Terminations are required at each end of the bus.
Set-up to use the serial bus lines on VME P1; how ever if P2 (6U card) is used then any number of buses may be added using the user defined pins.
Autobahn is set-up and controlled via the VME bus, but data is sent over the serial bus.

During cut-off the bus drivers are in Tri-State, via the termination resistors both sides of the bus are pulled to +3 volts.

Autobahn Bus Timing Diagram
Using 50 ohm termination to +3 volts

The Autobahn serial interface was defined in the original VME specification.
But reside on user defined pins, so may not be utilized [pins defined for any serial bus].
Pins B21 and B22 of the P1 connector are defined as SERDAT & SERCLK which could be used by Autobahn interface.
In fact it would take at least two VME cards in the same chassis using the serial interface to communicate via this interface.
In other words, don't expect to find an Autobahn residing on the the back of a VMEbus backplane.
In fact the same backplane pins were once used by the long abandon VMSbus back in 1994.
Note; the VME spec refers to the interface as an external specification but never makes reference to any document number.

Myrinet Bus Description

VITA 26-1998: Myrinet-on-VME Protocol Specification
The Myrient Bus uses either the P0 or P4 connectors on the VMEbus backplane and transmit via LVDS twisted pair cables to a DB37 connector.
The Myrient Bus is also available out the front panel.
The specification defines the Data Link Layer and Physical layers. Myrient provides CRC-8, with NRZI at 160Mbps.

VITA 26 VMEbus Front Panel Signals
pin# name pin# name pin# name pin# name
1 Rd+ 19 Sd+ 20 Rd- 37 Sd-
2 S0+ 18 R0+ 21 S0- 36 R0-
3 S1+ 17 R1+ 22 S1- 35 R1-
4 R7+ 16 S7+ 23 R7- 34 S7-
5 R6+ 15 s6+ 24 R6- 33 S6-
6 S2+ 14 R2+ 25 S2- 32 R2-
7 S3+ 13 R3+ 26 S3- 31 R3-
8 R5+ 12 S5+ 27 R5- 30 S5-
9 R4+ 11 S4+ 28 R4- 29 S4-

Pin 10 is omitted but must be grounded if the cable is longer than 10m.

Myrinet-on-VME 1.1 Draft was hosted on Myricom, Inc.
This standard may have fallen into disuse along with a number of VMEbus additions.

{Back to VME P2 Bus Index}


BusNet defines the Media Access Control (MAC), and Link Layer Control (LLC) 'layers'

BusNet Media Access Control (MAC) Specification (ANSI/VITA 19.1-1998)
BusNet Link Layer Control (LLC) Specification {ANSI/VITA 19.2-1998)

Related pages [but do not cover BusNet] include Protocol Terms and Protocol Abbreviations.

HIC Bus Description

ANSI/VITA13: VMEbus Pin Assignment for ISO/IEC 14575, IEEE 1355-1995 (H.I.C.), Specification

Basically the VITA 13 standard remaps the HIC signals [IEEE 1355] onto rows A and C [user defined] of the P2 connector.
See the HIC Bus page for additional information and descriptions.
However it doesn't appear that VITA 13 is released or an approved standard any longer.
There also appears to be no evidence that the standard was ever updated after the 1996 release date.
It could also be that IEEE 1355 was never updated or has also been withdrawn.

VXS Bus Description

VITA 41 { VXS Serial Connections on VME64x} VME P0 connector used to transfer high-speed switched serial data.
VXS Defines the Protocol and Mechanical characteristics.
VXS [VMEbus Switched Serial] allows for four differential serial pairs per direction, and up to two ports on each VMEbus card.

VXS.1 adds the 4X Infiniband protocol
VXS.2 adds the 4X Serial RapidIO protocol
VXS Board Manufacturers
VXS Board Description

{VME P2 Bus Index}

VME Bus Pin-Out

Signal assignments for the different connector arrangements:
P1 VMEbus connector pinout {IEEE 1014-1987}
P2 VMEbus connector pinout {IEEE 1014-1987}
{96 Pin Connectors: 3 Rows x 32 Pins}

P1 VMEbus connector pinout {ANSI/VITA 1-1994}
{160 Pin Connector: 5 Rows x 32 Pins}

P2 VMEbus connector pinout {ANSI/VITA 1-1994}
{160 Pin Connector: 5 Rows x 32 Pins}

Many standards listed on this page use the User Defined pins on the P2 connector.

SEM E {VITA 18-1997}
VME Bus Pin Assignments for Military {MIL-STD-1389} Format-E Boards and Backplanes

{Back to VME P2 Bus Index}

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Modified 6/13/15
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