VME (P2) Add on Buses

Versa Module Europa
IEEE 1014-1987



[SkyChannel Bus]
[RaceWay Bus] [Infiniband Bus] [P2CI Bus]
[FPDP Bus] [Autobahn Bus] [Myrinet Bus] [HIC Bus] [BusNet] [VXS Bus]
[VMEbus Pin-Out] [VME Bus Main Page]
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SkyChannel Bus Description

ANSI/VITA 10-1995 {SKYchannel Packet Bus on VME P2} used to transfer data @ 320 Mbytes/sec between VME boards over SKYchannel Backplanes. The SKYchannel Backplanes are daughter cards which plug into the P2 connector on the VME backplane. The signal are TTL compatible. SKYchannel defines the Data Link Layer, and Physical Layer [electrical interface].

Sky Computers


RACEWay Interlink Description

ANSI/VITA 5-1994 {RACEway Interlink} VME P2 Backplane Interconnect scheme
Defines the Protocol, Mechanical, and Electrical characteristics
The Raceway spec uses the user defined (row A and C) pins of the VME P2 connector. The additional rows added by VME64 (a and z) are not used.
The bus operates at 40MHz using 32 bit data transfers, possible transfer rate 480MBps. The bus operates on
adjacent slots on the VME bus as a Cross Bar Switch. Any number of slots may be interconnected, minimum is 4.

Technical Literature (RaceWay)
{Mercury Computer Systems Inc.}

{VME P2 Bus Index}


Infiniband Bus Description

Infiniband (High speed Serial Interconnect)
~VITA 31 VME64 P0 Backplane Interconnect scheme. Up to 8 Infiniband connections are allowed per P0 connector. Using a flat mating connector, with 3 grounds (outside/center pins) and 2 differential signal pairs.
Uses the Gigabit Ethernet connector / cable. Refer to the InfiniBand Bus page for more information.

{Back to VME P2 Bus Index}


P2CI Bus Description

VITA 27: {P2CI} PCI on P2 VME Compatible Interface. P2CI places the PCI Bus on the VME64 (5 row) P2 connector. The VME bus uses row B of the P2 connector, rows Z, A, C, and D are used for the P2CI bus. The bus speed remains the same for 33MHz; 132MBps [32 bit data], or 264MBps [64 bits data]. The P2CI standard does not reside on a 3U card because it uses the P2 [J2] connector. The P2CI interface may only reside on a 6U or 9U board. I think this specification was cancelled. Refer to the PCI Bus page for a detailed PCI bus description {This web site}. The electrical interface / IC drive levels will be the same as the PCI bus. All PCI interface ICs for the PCI bus are listed on then PCI Bus page. Note: the PCI Express Bus is set to replace the existing PCI bus implementation in the Personal Computer. PCI express is not compatible with the legacy PCI bus electrical standard. The PCI bus is single ended CMOS, while the PCI Express bus is differential LVDS.

{Back to VME P2 Bus Index}


FPDP Bus Description

ANSI/VITA 17 {FPDP; Front Panel Data Port} 32-bit synchronous front panel data bus @ 160MBytes/sec, differential PECL, over a 80 pin front panel connector.
The spec provides for a 1 meter ribbon cable. Can be used to connect 2 separate VME chassis. May be used with other bus types.

Front Panel Data Port (FPDP)
{FPDP.com}

---- {FiberXtreme} Serial FPDP approach, 105Mbps up to 10Km via a copper or fiber medium.

Serial FPDP operates at 1.0625GHz (Gbit Fibre Channel), or 2.48832GHz (SONET).
Serial FPDP will operate under a number of different connector/cable combinations; copper up to 30 meters, light up to 10 kilometers.

{Back to VME P2 Bus Index}


Autobahn Description

Differential serial bus (2 lines) running at 200MBps using PECL logic (+3 and +4 volts) via half duplex, NRZ. Data is sent in blocks, each block is 4 bytes. 50 ohm Terminations are required at each end of the bus. Set-up to use the serial bus lines on VME P1; how ever if P2 (6U card) is used then any number of buses may be added using the user defined pins. Autobahn is set-up and controlled via the VME bus, but data is sent over the serial bus.

Autobahn Timing
Using 50 ohm termination to +3 volts

During cut-off the bus drivers are in Tri-State, via the termination resistors both sides of the bus are pulled to +3 volts.

{VME P2 Bus Index}


Myrinet Bus Description

VITA 26-1998: Myrinet-on-VME Protocol Specification
The Myrient Bus uses either the P0 or P4 connectors on the VMEbus backplane and transmit via LVDS twisted pair cables to a DB37 connector. The Myrient Bus is also available out the front panel. The specification defines the Data Link Layer and Physical layers. Myrient provides CRC-8, with NRZI at 160Mbps.

Myrinet-on-VME 1.1 Draft {Myricom, Inc}

{Back to VME P2 Bus Index}


BusNet

BusNet defines the Media Access Control (MAC), and Link Layer Control (LLC) 'layers'

BusNet Media Access Control (MAC) Specification (ANSI/VITA 19.1-1998)

BusNet Link Layer Control (LLC) Specification {ANSI/VITA 19.2-1998)


HIC Bus Description

ANSI/VITA13: VMEbus Pin Assignment for ISO/IEC 14575, IEEE 1355-1995 (H.I.C.), Specification

See the HIC Bus page for additional information and descriptions.
{This Web Site}

{VME P2 Bus Index}


VXS Bus Description

VITA 41 { VXS Serial Connections on VME64x} VME P0 connector used to transfer high-speed switched serial data. Defines the Protocol and Mechanical characteristics. VXS [VMEbus Switched Serial] allows for four differential serial pairs per direction, and up to two ports on each VMEbus card.

VXS.1 adds the 4X Infiniband protocol
VXS.2 adds the 4X Serial RapidIO protocol
VXS Board Manufacturers
VXS Board Description

{VME P2 Bus Index}


VME Bus Pin-Out

P1 VMEbus connector pinout {IEEE 1014-1987}
P2 VMEbus connector pinout {IEEE 1014-1987}
{96 Pin Connectors: 3 Rows x 32 Pins}

P1 VMEbus connector pinout {ANSI/VITA 1-1994}
{160 Pin Connector: 5 Rows x 32 Pins}

P2 VMEbus connector pinout {ANSI/VITA 1-1994}
{160 Pin Connector: 5 Rows x 32 Pins}

Many standards listed on this page use the User Defined pins on the P2 connector.

SEM E {VITA 18-1997}
VME Bus Pin Assignments for Military {MIL-STD-1389} Format-E Boards and Backplanes

{Back to VME P2 Bus Index}


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Last Modified 2/16/08
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