Universal Test & Operations PHY Interface for ATM
Utopia: [af-phy-0017.000] describes the Universal Test &
Operations Physical Interface for ATM [UTOPIA] level 1 data path interface. It
describes the interface between the Physical Layer (PHY) and the upper
layer (ATM). The Utopia bus is the standard interface between
asynchronous transfer mode (ATM) link and PHY devices [interface between
ATM Layer (Data Link) and ATM PHY chips]. It covers rates from sub-100
Mbit/s to 155 Mbit/s and gives guidance for 622 Mbit/s. 8-bit wide data
paths use octet-level/cell-level handshake at 25 MHz.
Utopia Level 2: [af-phy-0039.000] is the Addendum to Level 1 and
describes support of a data rate of 622 Mbit/s over a 16-bit wide data
path at 33 and 50 MHz.
ATM is an asynchronous cell-switching and multiplexing bus,
providing scalable bandwidth to gigabits per second (Gbps). Using
Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH),
DS-3/E3 as the physical medium; ATM operates at 155Mbps over Fiber or STP
(shielded twisted-pair) ~ with 8B/10B encoding. Other physical
layers are possible.
ATM transfers data in (fixed size) Cells, with each
cell being 53 bytes in length.
The first 5 bytes contain cell-header
information, and the remaining 48 contain the "payload" (user
information).
An ATM network is made up of an ATM switch and ATM endpoints.
International Telecommunication Union, ITU [www.itu.int]
VMEbus International Trade Association, VITA
ATM Forum; Approved and Draft Specifications
Altera Corp. {IP Cores}
Integrated Device Technology Inc. 'IDT'
Lattice Semiconductor Corp. {UTOPIA PHY-TX}
Maxim {UTOPIA II bus interface}
National {Utopia-LVDS Bridge}
Xilinx {UTOPIA Level-3 Transmitter Interface Controller IP Core}
Zarlink Semiconductor {Clock Generation}
For all other IC manufacturers, see the Semiconductor page
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