RS-644 Bus

ANSI/TIA/EIA-644-95 Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits



[RS644 Description]
[LVDS ICs] [Standard Organizations ] [Connectors ]
[PECL to LVDS Conversion]
[LVPECL to LVDS Conversion]
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EIA-644 Description

EIA-644 Bus Circuit Inter-Connection Schematic, Half-Duplex
LVDS Interface Circuit

EIA/TIA-644 Balanced (differential) interface [LVDS]; defines the Electrical layer (Receiver and Transmitter) only.
Designed with an output voltage swing of 350mV at better then 400Mbps into a 100 ohm load, across a distance of about 10 meters. LVDS is only an Electrical spec - to be referenced by other specifications, it may be used with either a cable or PWB design. The type of cable determines cable length; Category 3 (CAT3) for 10m in length, CAT5 for longer runs (~20 meters @ 100Mbps, ~50 meters @ 50Mbps, ~100 meters @ 10Mbps). Ribbon cable may be used for sub meter runs. Also listed under IEEE 1596.3.

EIA-644 [LVDS] should not be confused with other (higher speed) Low-Voltage Differential circuits; ECL, PECL, LVPECL, or CML, all of which also use the term LVDS.

Other vendor types:
LVDS [EIA-644], Low Voltage Differential Signaling; 3.5mA drive, at 655Mbps max, Point-to-Point
BLVDS Bus LVDS, [Proprietary] 10mA drive designed to handle mulit-card low impedance backplane applications [One bus driver].
M-LVDS Multipoint LVDS [EIA-899], Addresses double terminated bus configurations also extends the common-mode range to +/-2 V. 11mA drive at 500Mbps max, 200/300Mbps typical for Multi-point
GLVDS Ground referenced LVDS, Places the driver output voltage offset closer to ground potential.
LVDM Low Voltage Differential Signaling Multi-Point, [Proprietary], 8mA with one bus driver.




For detailed LVDS design information;
see this LVDS Description page.

{LVDS Bus Index}


EIA-644 Bus Pull-up/Pull-Down Resistors

LVDS uses a single 100 ohm termination resistor at the Receiver side of the bus. The Receiver provides failsafe bias so Pull-up/down resistors are not required.
Noisy environments may require the addition of bias resistors.

The Pullup/Down Resistors (Idle-line failsafe) are used to keep the +/- inputs of the Receiver(s) inputs at a minimum of 200mV differential or higher.
Normally required once the system has reached it's quiescent state, when no drivers are driving the bus. Only one end of the bus requires the resistor network.

{LVDS Bus Index}


EIA-644 Bus Interface IC Manufacturers




Aeroflex UTMC {RAD hard IC Manufacturer}

Fairchild Semiconductor Corp. {Differential LVDS Repeater ICs}

Maxim Integrated Products, Inc.

National Semiconductor {Differential Bus Transceiver ICs- Receiver ICs -Driver ICs-SERDES Devices}

NXP {Clock Driver ICs}

ON Semiconductor {Clock Driver ICs}

Pericom Semiconductor Corporation {LVDS Drivers/Receivers/Crosspoint/Repeaters/Distribution IC Manufacturer}

STMicroelectronics {Differential Bus Transceiver ICs-Receiver- Clock Driver ICs}

Texas Instruments 'TI' {RS-644 Differential Driver/Receiver-8 bit Registered Transceiver ICs/SERDES Devices}

IC Manufacturers {All other device types}

{LVDS Bus Index}


LVDS Connector Manufacturers

Recall that EIA/TIA-644 does not define the connectors, so this list should be used as a guide.





Amphenol {LVDS Connector Manufacturer}

FCI

Methode Electronics {LVDS Connector Manufacturer}

Molex {LVDS Connector Manufacturer}

{LVDS Bus Index}


EIA/TIA-644 Standard Organizations

Telecommunications Industry Association; TIA [www.tiaonline.org]

Note the Electronic Industries Alliance {EIA} ceased operations on Feb 22 2011.

{LVDS Bus Index}


LVDS Standards

ANSI/TIA/EIA-644: Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits

TIA/EIA-899: Electrical Characteristics of Multipoint Low Voltage Differential Signaling (M-LVDS) Interface Circuits for Multipoint Data Interchange

Other specifications which use LVDS as the electrical interface include:
SATA, RapidIO, HyperTransport, and InfiniBand.

{LVDS Bus Index}


PECL to LVDS Conversion

PECL stands for either pseudo ECL or positive ECL.
Using the term PECL means that the negative voltage supply used with ECL have been replaced with a positive voltage.
Five volts and 3.3 volts are the most common used voltages, so they interface with normal TTL logic levels.

PECL conversion to LVDS {EIA644} Circuit Diagram
PECL to LVDS

LVPECL to LVDS Conversion

LVPECL conversion to LVDS {EIA644} Circuit Diagram
LV-PECL to LVDS





EIA-644 Bus Voltage Levels Comparison to other Differential Standards
LVDS [IEEE644] Interface level Comparison to other Differential Standards

Terms used in the graph;
PECL stands for Positive ECL which in many cases means ECL using a positive 5 volt supply, but really could be any positive voltage.
PECL is not a voltage standard but a convention of the usage of running ECL on 5 volts, dropping the uncommon negative voltage.
LVPECL stands for Low Voltage PECL and moves the PECL supply voltage down to the new standard 3.3 volt power supply.
The RS422 and RS485 could switch up to 6 volts, or may be set to switch at 3.3 volts.
The LVDS switching threshold is shown next, listed as 644, as IEEE644.
The two GTL standards [Gunning Transceiver Logic] are listed next.
Vol stands for Voltage Output Low, while Voh stands for Voltage Output High and are the switching ranges.

{LVDS Bus Index}


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Modified 2/26/12
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