A Brief Description of the PCI-X [Peripheral Component Interface] Bus;
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The Peripheral Component Interface [PCI-X] addendum is an
enhancement to the current 64 bit 66MHz PCI bus specification. The
minimum clock speed for PCI-X is 66MHz [PCI-X 66]. Additional bus
speeds include: PCI-X 133, PCI-X 266 and PCI-X 533 providing up to
4.3GBps [PCI-X 1066 in the works]. PCI-X is backwards compatible with
PCI; of course none of the
enhancements would be available and the best speed would revert to
66MHz. PCI-X provides for the same card form factor, pin-outs,
connector, bus widths, and protocols. Many of the changes relate to
bus operation, wait states and protocol enhancements, which is not
covered here. PCI-X still supports either 32 bit or 64 bit bus
widths. The DC switching Specifications look the same for PCI and
PCI-X. PCI-X does have a higher output AC driver current than PCI.
The PCI-X enhancement was never introduced into the Personal Computer market, although it did show
up in the [higher cost] server market. The PCI spec defines the Electrical requirements for the interface. No bus terminations are specified, the bus relies on signal reflection to active level threshold. The PCI bus operates either synchronously or asynchronously with the "mother Board bus rate. While operating asynchronously the bus will operate at any frequency from 66MHz down to (and including) 0Hz. Flow control is added to allow the bus to operate with slower devices on the bus, allowing the bus to operate at their speed. PCI is an unterminated bus, the signal relay on signal reflections to attain there final value. The PCI specification has been port-ed to a number of other form factors. These include: PCI: The original specification 'Peripheral Component Interface', @ Rev 2.1 PCI-X: The latest version 64 bits at: PCI-X 66, PCI-X 133, PCI-X 266 and PCI-X 533 [4.3GBps] cPCI, Compact PCI: PCI in a VME form factor, 3U/6U using 2mm connectors PC104-Plus: PCI add-on to the PC104 spec, ISA in a square form factor PISA: PCI add-on with PCAT in the ISA AT form factor P2CI: PCI on the VME64 P2 connector PMC: PCI on a Mezzanine Card, 'PMC' PMCx: PCI-X on a Mezzanine Card 'PMC' PXI cPCI for Instrumentation IPCI: Industrial PCI (Another version of cPCI} Serial PCI: PCI on a serial link Card Bus: 32 bit PCI on the PC Card (PCMCIA) Format Each of these additional specifications rely on the PCI spec., normally only the mechanical (form factor) definition changes. Unlike earlier PC buses, the PCI bus is processor independent. The (64bit) PCI bus is made up of the following (major) signals: Address/Data Bus: 64bit Address; 64bit Data, Time Multiplexed System Bus: 2bits; Clock/Reset Interface Control Bus: 7bits; Ready, Acknowledge, Stop. Parity Bus: 2 bits, 1 for the 32 LSBs and 1 for the 32 MSB bits Errors Bus: 2 bits, 1 for Parity and 1 for System Command/Byte Enable: 8 bits (0-3 @ 32bit, and 4-7@ 64bit Bus) 64MHz Control: 6 bits; (2) Enable/Running, (2) Present, (2) Ack/Req Cache: 2 Bits, Interrupt bus: 4 bits, JTAG Bus: 5 bits Power: +3.3v, GND. PCI-X does not support +5v [PCI], and I find no data reagrding +12, -12v [used in PCI] The Time Multiplexed Address and Data bus may exist as either 0 to 31 bits (32bits) or 0 to 63 bits (64bits) using the 64 bit expansion bus. Both the Address and Data line use the same bus, Address first then Data. 32 bit PCI may also use 64 bit addressing by using two address cycles; termed Dual Address Cycles (DAC), the low order address is sent first. Additional control bits are utilized once the bus is increased to 64 bits. The specification defines both a Reset line and a Clock line. The Clock may be either 33MHz or 66MHz. I believe the 66MHz clock rate is only defined for the 64bit bus width. A number of 'Handshake' lines exist to allow communication, i.e. Ready, and Acknowledge Two Parity lines are made available, one for the 32 bit bus width (bits 0 to 31) and an additional one for the 64 bit expansion (bits 32 to 63). Two error bits; I assume, 1 for the LSB 32 bits and one for the upper 32 bits. PCI cards for a personal computer differ from the ISA type by two important factor: Components a mounted on the reverse side of the card, The edge connector is more dense, shorter and the keys reside in different locations. |
The PCI bus [or PCI X bus] doesn't use Glue logic ICs, being
developed as a single chip interface bus.
So signal chip solutions or ASIC parts are the only PCI chips. PCI IC
manufacturers are listed below.
PCI is a CMOS bus, with no current flowing in the static state. The +5
volt interface uses standard TTL
switching levels VIH = 2v, VOH = 2.4v. The +3.3
volt interface uses VIH = 1.65v, VOH = 2.97v
Altera {PCI Cores}
AMCC {PCI Master Slave Controller IC, Target Controller}
Analog Devices {ISA-PCI Chip}
Cirrus Logic {PCI-Disk Controller ICs}
Infineon Technologies {PC Chips-DRAM Controller ICs}
Marvell {PCI chip set Manufacturer}
PLX Technology Inc. {133MHz PCI-X-to-PCI-X [P2P] bridge Chip}
QLogic {PCI ICs - SBus}
Silicon Image Inc {Ultra ATA/100 PCI to ATA Host Controler ICs}
Texas Instruments {PCI Bridges-Controller ICs}
Tundra Semiconductor Corp. {PCI or PCI-X [P2P] bridges to RapidIO [Tsi400]}
Xilinx {FPGA Core; PCI-X for 64-bit designs running at speeds up to 133 MHz}
PICMG {PCI Industrial Computer
Manufacturers Group}
PCISIG {Peripheral Component
Interconnect - Special Interest Group}
PCI Local Bus Specification:
PCI version 1.0 was developed by Intel in 1991 but not released by
a Standards body.
PCI revision 2.0; released in 1993; 32-bit, 33MHz bus.
PCI revision 2.1; released in 1995; 32-bit, 33MHz / 64-bit, 66MHz,
Universal PCI for 3.3v or 5v cards
PCI revision 2.2; released 1998; minor clarifications /
enhancements.
PCI revision 2.3; released in 2002; removed 5v only cards
PCI revision 3.0; released in 20xx; removed 5 volt interfaces
altogether.
PCI in other Form Factors:
PCI-X Addendum to PCI Local Bus Specification (Ver 1.0)
Mini PCI Bus Specification (Ver 1.0)
Small PCI Specification (Ver 1.5a)
PCI-to-PCI Bridge Specification (Ver 1.1)
PCI Model Design Guide (Ver 1.1)
PCI Bus Power Management Specification (Ver 1.1)
PCI Hot-Plug Specification (Ver 1.0)
PCI Bios Specification (Ver 2.1)
HiRelPCI An Extensible High Reliability Extended PCI Bus (Draft
0.65)
PXI Specification {Ver 1.0}
PISA Bus (Ver 1.8)
PISA-2 (Ver 1.2) PISA Back Plane with 1 PISA and 1 ISA Slot
CompactPCI Specification (Ver 2.0 R2.1 - Short Form)
AVX {Connector Manufacturer}
FCI {Connector
Manufacturer}
Meritec {PCI Cable Assemblies}
Engineering Design Key words: PCI, PCI-X, PCI X, PCI-Express, Peripheral Component Interconnect, Electrical layer, Standard, Interface Standard Data Bus, Specification, Spec, Interface, IC, Physical Interface, Description, Personal Computer, PC, Local Bus
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