Other Buses

[Multibus] [STD 32] [FastBus] [AMR-CNR]
[JTAG] [IP Core]
[Main Data Bus Description Page]

Multibus Description

Multibus I: IEEE-796: Microcomputer System Bus; First released by Intel in 1974. The cards did not use front panels, and they used card edge fingers as the connectors (similar to ISA/PC-AT cards).
Companies like Northwest Technical still provide "End of Life" products for Multibus. This bus is obsolete and should not be used for new designs.

Multibus II: IEEE-1296 32 Bit Bus, at 80MBps. Card sizes are 3U x 220mm, and 6U x 220mm. These cards are larger then the VME Eurocard sizes which are 3U/6U x 160mm. Multibus uses TTL ('Fast' series) gates for drivers and the Backplane Connectors are DIN41612 type C. Multibus II is not yet considered obsolete, but considered mature; however it is not recommended for new designs.

Multibus I, II and III Form Factor
Multibus Board Size and dimensions

FastBus Description

IEEE Std 960-1993 Defines the Mechanical, Electrical, and Protocol. The link indicates a 32 bit ECL interface for data and address buses. ECL IC manufacturers are listed on the Standard Logic Manufacturers page. Fastbus was released in 1986, while the current version dates to 1993

"FASTBUS is a sophisticated data acquisition system standard developed by the U.S. NIM Committee in collaboration with the European ESONE Committee (ANSI/IEEE STD 960-1986). FASTBUS was designed to keep features of older important standards while extending the capabilities of data acquisition systems.

Essentially, the FASTBUS backplane is intended to be an extension of a computer backplane. By its nature, therefore, it is an expandable system. The backplane is called a "Segment". Connections between segments are made by an interface, called a Segment Interconnect (SI). An SI in one segment is connected to a SI in another segment by a Cable Segment. The Segment Interconnect can be either a Master or Slave, depending on the operation it is performing. Moreover, it can be a Master on the FASTBUS Segment and simultaneously a Slave on the Cable Segment. The designations Master and Slave here are dynamic, in that the designation is defined by the role played by the SI at some given time.

FASTBUS permits multiple masters to have access to the segment. The standard provides a protocol for arbitration when more than one master requests control of the segment. Once master-ship is granted, the Master may then proceed to establish a communications "lock" with any other device on the segment which will act as a Slave. Alternatively, the Master may broadcast a message to all Slaves which respond to the broadcast.

The integrity of communication between Master and Slave modules is ensured via a hand-shaking scheme. This frees the standard from a speed requirement. That is, communication occurs at whatever speed the Master/Slave system will support. This, of course, is not the case with broadcast commands where a Master talks to all Slaves in a segment, nor is it true for hardware block transfers where the Master must be able to operate as fast as the fastest Slave. So while there are cautions required for use of FASTBUS, the versatility and expandability is sufficient to meet the most demanding requirements of data acquisition systems." extracted from: fermilab

VERSAbus Description

VERSAbus; defined by Motorola Corporation in 1979 for its 68000 microprocessor.
VMEbus was originally a combination of the VERSAbus electrical standard, and the Eurocard mechanical form factor.
VERSAbus has been obsolete for some time now.


PC Mother Board to Card interface bus. Smaller I/O connectors.

AMR: Audio/Modem Riser. Specification defines a hardware scalable OEM mother board riser board and interface, which supports both audio and modem.
An MR slot will provide a Modem function, while an AMR slot will provide both an Audio and Modem function
CNR: Communication and Networking Riser.
ACR: Advanced Communication Riser.
PC Riser card interfaces are now listed on the Riser Card Bus Description Page, refer to that page for additional information.


IEEE Std 1596-1992 SCI (Scalable Coherent Interface)
SCI is a scalable network, nodes are interconnected in a point-to-point unidirectional link [ring]. The bandwidth grows with the number [concurrent] nodes used. SCI links are operate at 1 Gbps [serial], or 1 GBps [16-bit parallel], using a 250-MHz bi-phase clock over fiberoptic or twisted-pair wires. Physical SCI controllers use LVDS signaling levels for 16 and 8 bit wide links. Refer to the main SCI Bus page.

HubLink Bus

I think HubLink is used on Intel Corp. chipsets to interconnect their devices. I believe it's 8 bits wide running at 66MHz. There is also a Hublink 2 interface which is 16 bits wide, running at 66MHz. The HubLink interface has a maximum throughput of 266 MB per second, roughly 2.2 Gbps. A more complete description appears on the IC bus page, see the Buses Icon at the bottom of the page, then IC Buses.


NIM: Nuclear Instrumentation Methods, DOE/ER-0457. NIM modules are 8.75" high by a multiple of 1.35" wide;
Single width modules: 8.75" high x 1.35" wide
Double width modules: 8.75" high x 2.7" wide

The Chassis is called a crate and will accommodate 12 single wide modules. The power supply will produce +6 V, -6 V, +12 V, -12 V, +24 V, and -24 Volts.

More Bus Types

AMXbus: Analog Expansion Bus. A proprietary interface developed by VMIC. The AMXbus is a proprietary VME P2 backplane used to support the VMIC series of ADC and DAC boards. The AMXbus back-plane is supplied as 5, 9, or 19 slots.

SRTbus: Synchro / Resolver Test Bus. A proprietary interface developed by VMIC. The SRTbus is a proprietary VME P2 backplane used to support the VMIC series of Synchro and Resolver boards. The SRTbus back-plane is to test [as a built in Test] bus for the Synchro / Resolver boards.

CAMAC: Computer Automated Measurement And Control. The chassis [Crate] contains 25 slots. The bus Controller resides in Slot 25

FED-STD-1020 Telecommunications: Electrical Characteristics of Balanced Voltage Digital Interface Circuits (adopts the requirements of EIA-RS-422)

FED-STD-1030 Telecommunications: Electrical Characteristics of Unbalanced Voltage Digital Interface Circuits (adopts the requirements of EIA-RS-423)

IEEE-1073 Point of Care Medical Device Communication Standards

Many of the bus types listed on this page require additional work to be listed on their own page, however most buses are obsolete and will not be listed on a new page. Because some buses have been obsolete for so long no additional work is planed and are listed here for completeness. A few bus types that were listed on this page have moved to their own pages. Use the Main Data Bus Description Page to locate these buses, or click the 'Home' icon below to search for that bus name.

{top of Other Interface Buses}

Larry's Web Page

Electronic Parts and Equipment Distributors Electronic Component Manufacturers OEM Electronic Equipment Manufacturers EDA Software Producers CAD/CAE Software Engineering Standards, EE Publications Interface/Embedded Computer Bus Electronic Engineering Design Data Engineering Reference Information.
DistributorsComponents Equipment Software Standards Buses Design Reference

Modified 6/13/15
© 1998 - 2016 All rights reserved Larry Davis