ANSI/TIA/EIA-644 Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits

General LVDS Description

EIA-644 Interface Circuit and Electrical layer implementation
LVDS Interface Circuit

EIA/TIA-644 [LVDS] is a differential [Balanced] interface which defines the Electrical layer only (Receiver and Transmitter). The Physical [PHY] or Protocol layers are not defined. LVDS may be used with either a cable or board [PWB] interface [bus], and may be referenced by other specifications as their Electrical interfaces.

LVDS is designed with an output voltage swing of 350mV with speeds at better then 400Mbps into a 100 ohm load, across a distance of about 10 meters. As with all buses, the type of cable determines cable length [or bus speed]; Category 3 (CAT3) for 10m in length, CAT5 for longer runs (~20 meters @ 100Mbps, ~50 meters @ 50Mbps, ~100 meters @ 10Mbps). Ribbon cable may be used for sub meter runs. LVDS Edge rates are 1V/nS, Output voltage is 350mV [250mV min., 450mV max.]. The center voltage is 1.2 volts. LVDS uses a current-mode driver output from a 3.5mA current source. This drives a differential line that is terminated by a 100 ohm resistor, generating about 350 mV across the receiver. The +350mV voltage swing is centered on a 1.2V offset voltage.

For additional information and application notes, use the page links below. Some of which were used to prepare this page:

Backplane Designer's Guide {Fairchild Semiconductor}

Detailed LVDS Design Description

LVDS Electrical Interface
LVDS Single Link Interface Circuit

The basic LVDS interface is a single differential link in either one or both directions. Each link requires a termination resistor at the far [receiver] end. The nominal resistor values used is 100 ohms, but would depend on the cable or PWB trace impedance used. Refer to the LVDS notes page [Termination vales] for addition information. This page assumes a 100 ohm trace or cable bus. LVDS is a scalable bus; one uni-directional link or multiple links may be used.

LVDS Multi-Drop Bus implementation Circuit
LVDS Multi-Drop Interface Circuit

LVDS may also be used on a Multi-Drop bus, using one driver and multiple receivers. keep stub lengths below 12mm for each receiver.

LVDS Center Multi-Drop Bus implementation Circuit
LVDS Multi-Drop [Center] Interface Circuit

When higher speeds, or when longer traces are used a center driver may be used (if practicable). The center driver allows the traces between the driver and each of the receivers to remain near the same length. The center driver keeps the PWB trace delay from one receiver to the next about the same. Bi-directional LVDS [half-duplex on a single pair of wire] requires a termination resistor at each end of the line. The addition of another resistor lowers noise margin that in tern reduces the maximum bus distance to under 10 meters. For this application use Bus LVDS [B-LVDS] instead of normal LVDS.

EIA644 Bus Stub Length
LVDS Multi-Drop [Center] Interface Circuit

The Multi-Drop picture just shows drivers and receivers hanging off a bus (length). How ever, another concern is stub length. As these devices are connecting off the main bus line they produce a stub. The example just above shows one method of keeping the stub length to a minimum on a PWB. If the receivers on the PWB can not be placed near the in coming lines (near the connector), because the driver side trace becomes to long. An additional set of differential receivers may be placed at the connector keeping the stub length short, which would then drive the following receivers.

LVDS Clock driver Bus circuit implementation
LVDS Clock Driver Interface Circuit

For on-board clock distribution there are 1 to x [low skew] clock driver devices

LVDS Bus Interface ICs

EIA Interface Levels
Chart of Interface logic, voltage switching levels

For a listing of OEM LVDS Interface device manufacturers see the main EIA/TIA-644 page

Note there are a number of different connectors used to transfer LSDS signals.

LVDS Pull-up/Pull-Down Resistors

LVDS uses a single 100 ohm termination resistor at the Receiver side of the bus. The Receiver provides failsafe bias so Pull-up/down resistors are not required. Noisy environments may require the addition of bias resistors.

The Pullup/Down Resistors (Idle-line failsafe) are used to keep the +/- inputs of the Receiver(s) inputs at a minimum of 200mV differential or higher. Normally required once the system has reached it's quiescent state, when no drivers are driving the bus. Only one end of the bus requires the resistor network.

LVDS Standard Organizations

ANSI/TIA/EIA-644: Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits

Electronic Industries Alliance 'EIA' ...... Telecommunications Industry Association 'TIA'

PC motherboard

Distributor rolodex Electronic Components Electronic Equipment EDA CDROM Software Engineering Standards, BOB card Cabled Computer Bus Electronic Engineering Design Table Conversion DB9-to-DB25.
DistributorsComponents Equipment Software Standards Buses Design Reference

Modified 2/26/12
Copyright © 1998 - 2012 All rights reserved Leroy Davis