I2C Bus / Access Bus

[I2C Description] [Access Bus Description]
[Interface ICs] [Online Standards]

I2C Bus Description

I2C bus [Inter-IC Bus] or [IIC Bus] was originally designed to be a battery control interface. The I2C bus uses a bi-directional Serial Clock Line [SCL] and Serial Data Lines [SDA]. Both lines are pulled high via a resistor [Rp]. Resistor Rs is optional, and used for ESD protection for 'Hot-Swap' devices. No other lines are specified. Three speed modes are specified: Standard; 100kbps [Bits per Second], Fast mode; 400kbps, High speed mode 3.4Mbps. I2C, due to its two-wire nature (one clock, one data) can only communicate half-duplex. The maximum bus capacitance is 400pF, which sets the maximum number of devices on the bus and the maximum line length. The interface uses 8 bit long bytes, MSB [Most Significant Bit] first, with each device having a unique address. Any device may be a Transmitter or Receiver, and a Master or Slave. Data and clock are sent from the Master ~ valid while the clock line is high. The link may have multiple Masters and Slaves on the bus, but only one Master may be active at any one time. Slaves may receive or transmit data to the master. I2C defines the electrical layer and protocol, and was developed by Philips Semiconductors. VDD may be different for each device, but all devices have to relate their output levels to the voltage produced by the pull-up resistors [RP].
Newer I2C Serial Interface page.

I2C Bus Interface Circuit
IIC Circuit

Data on the data line only changes when the clock line is low. However if SDA drops while SCL is high a start of frame is indicated. Also if SDA rises while SCL is high than a stop condition is indicated. The Start condition indicates a start of frame and the Stop condition indicates an end of frame. Each transfer on the I2C is 9 bits long, eight data bits followed by a '1' bit. The listener acknowledges the receipt of the byte in one of two ways; the listener may over write the '1' bit with a '0' bit indicating ready for more data. or leaving the trailing '1' indicating not ready for data.

The Master [talker] always generates the clock and the message. An I2C message begins with a Start bit, followed by a 7 bit Slave address and then a direction bit ['1' for Read, '0' for Write].

Access Bus Description

Access.Bus is a low speed serial bus aimed at the PC (serial bus) market. Access.Bus uses the I2C bus as the electrical hardware interface. A four pin modular type connector and a shielded 4 wire cable is called out in the specification. ACCESS.bus operates at 100 Kbps with a maximum cable length is 10 meters, however a repeater may be added to increase the bus length. Access.Bus uses the same signals as the I2C bus, and adds ground and power, pin out below. The specification is controlled by the ACCESS.bus Industry Group (ABIG).

Access.Bus Pinout
Pin 1: GND, Black(#26AWG) [AWG: American Wire Gauge]
Pin 2: SDA [Send Data], Green (#28AWG)
Pin 3: +5v, Red (#26AWG)
Pin 4: SCL [Serial Clock], White (#28AWG)
Shield: Connected only to the host connector shield and host ground

The Access.Bus specification [see below] also calls out pull-up and serial resistors located on the host.

I2C Bus Interface IC Manufacturers

Hendon Semiconductor {2-wire bi-directional Bus Buffer}

Maxim {12-Bit Plus Sign Temperature Sensors with SMBus/I2C-Compatible Serial Interface}

NXP {I2C Bus}

Many ICs have the I2C interface including some processors and controllers.

IC Chip Manufacturers {All other types}

I2C and AccessBus Standards Info

The I2C-Bus Specification Version 2.1 Jan. 2000
The I2C standard was released by Philips, which is now NXP

Refer here for the new I2C Serial Interface page.

AccessBus Protocol Specification
{Micro Computer Control Corp}

PC motherboard

Distributor rolodex Electronic Components Electronic Equipment EDA CDROM Software Engineering Standards, BOB card Cabled Computer Bus Electronic Engineering Design Table Conversion DB9-to-DB25.
DistributorsComponents Equipment Software Standards Buses Design Reference

Modified 6/13/15

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