HyperTransport Interface Circuit
[HyperTransport Bus Description]
[HyperTransport Interface ICs]
A Point-to-Point bus with [at least] two unidirectional links, formally
known as Lightning Data Transport (LDT). Uses 2, 4, 8, 16 or 32 bits [in
each direction]. Data rate is 800MBs/per 8 bit pair(s) with a 400MHz
clock. The aggregate bandwidth in both directions is 1.6GBps for 8 bit
[bi-directional] pairs. 16 bi-directional pairs brings the data rate up
to 3.2GBps per direction. HyperTransport [HT] also has an I/O Link
specification which defines the link protocol. HyperTransport is
packet-based. The figure below shows one uni-directional link, in
HyperTransport their is an identical uni-directional link coming back
from the far end.
The HyperTransport 3.0 Specification provides 41.6 GB/s Aggregate Bandwidth.
HyperTransport was started to complement the PCI bus; how ever it would appear that the interface is moving toward the server market with Serial PCI [PCI-Express] maybe becoming (and later replacing) the complement to PCI on Personal Computer Buses. The HyperTransport bus is used in conjunction with AMD processors on Desktop PCs. Early on, HyperTransport was predicted to compete against PCI-X and Infiniband. Now that it's a few years later HyperTransport has a place of it's own, and on AMD Mother Boards which uses a bridge to communicate to PCI-X [high-end PCs] / PCI [Desktops] buses.
The HyperTransport interface uses LVDS [Low Voltage Differential Signaling], refer to the EIA-644 page for addition information on LVDS.
HyperTransport in IP Core {Altera}
uP w/ HyperTransport interface {AMD}
PLX Technology Inc. {HyperTransport Bridge ICs}
HyperTransport in IP Core {Xilinx}
Engineering Design Key words: HyperTransport, Lightning Data Transport (LDT), Electrical Standard, Differential Interface Standard, Specification, Spec, Interface, IC, Description, Personal Computer Interface, PC Server, LVDS Phy, IC Manufacturers
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