HyperTransport Interface Circuit
[HyperTransport Bus Description]
[HyperTransport Interface ICs]
A Point-to-Point bus with [at least] two unidirectional links, formally
known as Lightning Data Transport (LDT). Uses 2, 4, 8, 16 or 32 bits [in
each direction]. Data rate is 800MBs/per 8 bit pair(s) with a 400MHz
clock. The aggregate bandwidth in both directions is 1.6GBps for 8 bit
[bi-directional] pairs. 16 bi-directional pairs brings the data rate up
to 3.2GBps per direction. HyperTransport [HT] also has an I/O Link
specification which defines the link protocol. HyperTransport is
packet-based. The figure below shows one uni-directional link, in
HyperTransport there is an identical uni-directional link coming back
from the far end. Now with any standard, HT gets a revision every few years
The HyperTransport 3.0 Specification provides 41.6 GB/s Aggregate Bandwidth.
While the newest HT 3.1 specification takes the maximum bandwidth to 51.2GB/s.
HyperTransport [HT 1.x] Max Clock Speed 800MHz, Maximum Bandwidth 12.8 GB/s, [including 1.03, 1.04, 1.05, and 1.1]
HyperTransport [HT 2.0] Max Clock Speed 1.4GHz, Maximum Bandwidth 22.4 GB/s
HyperTransport [HT 3.0] Max Clock Speed 2.6GHz, Maximum Bandwidth 41.6 GB/s
HyperTransport [HT 3.1] Max Clock Speed 3.2GHz, Maximum Bandwidth 51.2 GB/s
Hypertransport HNC High Node Count, protocol
HyperTransport was started to complement the PCI bus; how ever it
would appear that the interface is moving toward the server market with
Serial PCI [PCI-Express] maybe becoming (and later
replacing) the complement to PCI on Personal Computer Buses. The
HyperTransport bus is used in conjunction with AMD processors on Desktop PCs. Early
on, HyperTransport was predicted to compete against PCI-X and Infiniband. Now that it's a few years
later HyperTransport has a place of it's own, and on AMD Mother Boards which
uses a bridge to communicate to PCI-X [high-end PCs] / PCI [Desktops] buses.
UNlike PCIe, HTB does not use 8B/10 an so does not have that over head requirement.
The HyperTransport interface uses LVDS [Low Voltage Differential Signaling], refer to the EIA-644 page for addition information on LVDS.
HyperTransport Interfaces;
Altera {HyperTransport in IP Core}
AMD {uP w/ HyperTransport interface}
DRC {Socket 940 coprocessor}
PLX Technology Inc. {HyperTransport Bridge ICs}
HyperTransport in IP Core {Xilinx}
A related standard is called HyperTransport eXpansion [HTX]. This specification places the HyperTransport Interface on a peripheral slot-based card or interface, HyperTransport on a peripheral card [same size as a PCI card]. The current clock speed of an HTX interface [HTX3] runs at 2.6GHz, at a bandwidth of 20.8 GB/s [with 2 unidirectional 16-bit double data rate [DDR] HyperTransport links]. HTX motherboards used the same mechanical connector as PCIe [1x and 16x], although it's rotated. These HTX cards are meant for Servers, Blades, Workstations and so on. Riser boards may also be used. Also refer to HTX Server Board Manufacturers.
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