Futurebus Description, Pinout, Signal Name, and Manufacture links. Futurebus+

Futurebus

IEEE-896

[Futurebus Description]
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Futurebus Description

Futurebus and then Futurebus+ is a back-plane bus specification which defines both the Physical and Electrical layers.
The Futurebus bus width started at 32 bits wide, but now with Futherbus+ the width may be up to 256 bits.
Bus widths of 32, 64,128 and 256 are possible at a clock rate of 100MHz.
The data may transfer with either asynchronous or source-synchronized protocol. When operating with 256 bit transfers, the data rate may be as high as 3200MBps.
The FutureBus card size is defined as 300mm x 300mm, and uses 2mm style connectors.
Bus (card) addressing is fixed by the card slot, with each card receiving a unique fixed 5bit address number
Data transfer uses a broad-cast approach for the addressing. The Master out-puts the address in combination with an AS line,
and then waits until (each) all cards have asserted the Ack line. Once all cards have Ack-ed, data is output with the data valid strobe DS.
The recipient then asserts the data ack line (DK)

I do not believe that Futurebus was ever adopted by any one, and Futurebus+ [Futurebus-Plus] never saw wide spread usage. The Futurebus connectors are still used and may be procured, but I can't find many Integrated Circuit vendors producing parts.

{Future Bus Index}

Futurebus Bus Pin Out

AD[63 .. 0]*: 64 bit address bus during the address phase, then 64 bit data bus during data phase. AI*: Address Inverse Line. Used by the Slave to indicate it is still examining connection phase information, or has begun the disconnection phase. This is the inverse of AK*. AK*: Address acKnowledge line, used by the Slave to indicate it is still examining disconnection phase information, or has begun the connection phase. This is the inverse of AI*. AS*: Address Synchronization line. Asserted by the bus Master. BP[31 .. 0]*: Byte Parity. A parity bits is asserted if the number of asserted signals in the byte lane is even. CA[2 .. 0]*: CApability lines. CA0* [TS*]: Transaction Speed. During packet transfers indicating that the transfer mode is using the faster of the two modes. CA1* [CO*]: COmpelled signal. Asserted, in the connection phase, indicates that the default compelled data transfer mode is used for the transaction. CA2* [SR*]: Split Response signal. Driven by the Slave or MAster to indicate a split transaction. CM[7 .. 0]*: CoMmand lines. CM0* [LK*]: LocK signal. Used to indicate that the locked resource is to remain locked. CM0* [PR*]: Packet Request signal. Used by the Slave to indicate that another packet with address immediately subsequent to the just completed packet will be requested. CM[2 .. 0]* [DL2..0*]: Data Length signal. Encode values indicating the length of a data transfer. CM[3 .. 0]* [TC3..0*]: Transaction Code signals. Indicates what type of transaction will follow. CM[2 .. 0]* [LC2..0*]: Lock Command signal. Used to indicate which of the defined special lock commands should be used following transaction. CM4* [SW*]: Slave Write signal. A reflection by the bus Master of the connection phase value of IV*. CM[6 .. 5]* [DW1..0*]: Data Width signal. Encode whether 32, 64, 128, or 256 bit data transfers are being used. Asserted during the connection phase only. CM7* [AW*]: Address Width Line. Indicates 64 bit transfers when asserted, other wise indicates 32 bit transfers. CP*: Command Parity. This line is asserted if the number of bits asserted in CM[7..0]* is even. D[256 .. 64]*:Used to extend the data bus. These lines are unused during 32 or 64 bit data transfers. DI*: Data Inverse line. Driven by the slave, asserted at the beginning of each even data beat and negated to end each odd data beat. DK*: Data acKnowledge. Driven by the slave, asserted at the beginning of each odd data beat and negated to end each even data beat. DS*: Data Synchronization line. Asserted by the bus master indicating the start of a new data phase. ET*: End-of-Tenure. Used to indicate that the current MAster has completed tenure GA[4 .. 0]*: Geographical Address. Indicates, during reset, which slot the card occupies. GR*: GRant signal. Driven to each slot individually by the central arbiter to indicate that the card driving the RQ0* or RQ1* is the new Master. MR* [WR*]: WRite signal. Driven by the bus Master to indicate whether the bus will be reading or writing. PE*: PreEmption signal. Asserted by the central arbiter to indicate to all modules that a Master with a higher priory than the current Master is requesting the bus. RE*: REset signal: Systems reset, Live Insertion, or re-initialized. RQ0*: ReQuest level 0 signal. Used to request Bus Master ship. RQ1*: ReQuest level 1 signal. Used to request Bus Master ship. ST[7 .. 0]*: Status lines. ST0* [TE*]: Transaction Error signal. Warns of errors that are fatal to the transaction as a whole. ST1* [BS*]: Busy signal. Asserted by the slave. ST1* [ED*]: End of Data signal. Carried during the data and disconnection phase. ST2* [SL*]: SeLected signal. Asserted by the slave indicating that the selected resource resides on it's card. ST3* [BC*]: Local Broadcast signal. Asserted by the Slave to indicate that this is a transaction to a broadcast resource. ST4* [TF*]: Transaction Flag. ST5* [IV*]: InterVention signal. Used in a cache coherent environment. Used by other modules to supply updated data. ST6* [BE*]: Beat Error signal. Asserted is a parity error occurs in the connection or data phase. ST7* [WT*]: WaiT signal. Driven by the slave to indicate it is unable to respond to the requested transaction. TG[7 .. 0]*: Tag lines. (undefined) TP*: Tag Parity line. Parity signal for the Tag lines. TP* is asserted when the number of bits in TG is even. Extracted from DS3805 Futurebus+ Protocol Controller, Data Sheet; National Semiconductor @1992

{FutureBus Index}

Futurebus On-Line Standards Information

896.1: Futurebus+ Logical Layer Specifications
896.2: Futurebus+ Physical Layer Specifications
P896.3: Futurebus+ System Configuration Guide
1014.1: VME/Futurebus+ Bridge

Institute of Electrical and Electronics Engineers, Inc. IEEE

{Back to Futurebus Index}

Future Bus Interface IC Vendors

The Futurebus (and Future bus+) specification uses Backplane Transceiver Logic (BTL) Family of devices - ABT and FB series of parts. A number of companies offer these series of parts; however only TI offers Futurebus specific chips.

Click for a larger Image of a Logic Voltage Threshold Chart

Texas Instruments 'TI'

BTL Device Manufactures {This Web Site}
IC Manufacturers {All other types} {This Web Site}

{Futurebus Interface Index}

Futurebus Connector Manufacturers

IEC 1076-4-104: 2mm connectors, Hard Metric Packaging Specification.
FutureBus connectors, which use 2mm style have a mating distance of 10mm. cPCI also use 2mm connectors with a mating distance of 12.50mm, matching the 96 pin DIN 41612 connectors used with other EuroCard packaging [IEC 273 or IEEE 1101, 1101.10], like VMEbus. However; because the mating distance is different, FutureBus connectors are not compatible with cPCI or VME connectors.

CTS Corporation
{2mm Pitch Futurebus Connector, Unshielded, Shielded}

Foxconn
{Future Bus 2mm Conn 4Row Power Header, Signal Header, Receptacle, 5 Row}

Harwin Plc
{2.00mm Pitch Futurebus Connectors 8/9 Row Housing Unshielded/Shielded 8x12, 9x12}

Harwin Plc
{2.00mm Pitch Futurebus Connectors}

ITT Industries
{2mm Futurebus Connectors, 4 and 5 row / Hybrid and Shroud Coax Contacts}

Molex Inc.
{Futurebus+ Connectors}

tyco Electronics
{2mm Centerline Futurebus+ Connector Manufacturer}

Top Lengths: 5.00, 5.75, 6.50, 7.25, 8.00mm
Tail Lengths: 4.30, 12.10, 13.60, 15.10, 15.60, 17.00mm

{Back to Futurebus Index}

Design Key words: Futurebus, Futurebus+, Backplane bus, Parallel bus, Futurebus defines the Physical and Electrical layers, IEEE-896, Physical, Mechanical, Size, Card dimensions, Board dimensions, Type, Description, Brief, ICs, Integrated Circuits, Chassis, COTS, Cards, Vendor, Vendors, Products, Manufacturers, specification, Spec, Parallel bus, Open Collector, Pinout, Pin Out, Signal Name.


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