Futurebus

AD[63 .. 0]*: 64 bit address bus during the address phase, then 64 bit data bus during data phase. AI*: Address Inverse Line. Used by the Slave to indicate it is still examining connection phase information, or has begun the disconnection phase. This is the inverse of AK*. AK*: Address acKnowledge line, used by the Slave to indicate it is still examining disconnection phase information, or has begun the connection phase. This is the inverse of AI*. AS*: Address Synchronization line. Asserted by the bus Master. BP[31 .. 0]*: Byte Parity. A parity bits is asserted if the number of asserted signals in the byte lane is even. CA[2 .. 0]*: CApability lines. CA0* [TS*]: Transaction Speed. During packet transfers indicating that the transfer mode is using the faster of the two modes. CA1* [CO*]: COmpelled signal. Asserted, in the connection phase, indicates that the default compelled data transfer mode is used for the transaction. CA2* [SR*]: Split Response signal. Driven by the Slave or MAster to indicate a split transaction. CM[7 .. 0]*: CoMmand lines. CM0* [LK*]: LocK signal. Used to indicate that the locked resource is to remain locked. CM0* [PR*]: Packet Request signal. Used by the Slave to indicate that another packet with address immediately subsequent to the just completed packet will be requested. CM[2 .. 0]* [DL2..0*]: Data Length signal. Encode values indicating the length of a data transfer. CM[3 .. 0]* [TC3..0*]: Transaction Code signals. Indicates what type of transaction will follow. CM[2 .. 0]* [LC2..0*]: Lock Command signal. Used to indicate which of the defined special lock commands should be used following transaction. CM4* [SW*]: Slave Write signal. A reflection by the bus Master of the connection phase value of IV*. CM[6 .. 5]* [DW1..0*]: Data Width signal. Encode whether 32, 64, 128, or 256 bit data transfers are being used. Asserted during the connection phase only. CM7* [AW*]: Address Width Line. Indicates 64 bit transfers when asserted, other wise indicates 32 bit transfers. CP*: Command Parity. This line is asserted if the number of bits asserted in CM[7..0]* is even. D[256 .. 64]*:Used to extend the data bus. These lines are unused during 32 or 64 bit data transfers. DI*: Data Inverse line. Driven by the slave, asserted at the beginning of each even data beat and negated to end each odd data beat. DK*: Data acKnowledge. Driven by the slave, asserted at the beginning of each odd data beat and negated to end each even data beat. DS*: Data Synchronization line. Asserted by the bus master indicating the start of a new data phase. ET*: End-of-Tenure. Used to indicate that the current MAster has completed tenure GA[4 .. 0]*: Geographical Address. Indicates, during reset, which slot the card occupies. GR*: GRant signal. Driven to each slot individually by the central arbiter to indicate that the card driving the RQ0* or RQ1* is the new Master. MR* [WR*]: WRite signal. Driven by the bus Master to indicate whether the bus will be reading or writing. PE*: PreEmption signal. Asserted by the central arbiter to indicate to all modules that a Master with a higher priory than the current Master is requesting the bus. RE*: REset signal: Systems reset, Live Insertion, or re-initialized. RQ0*: ReQuest level 0 signal. Used to request Bus Master ship. RQ1*: ReQuest level 1 signal. Used to request Bus Master ship. ST[7 .. 0]*: Status lines. ST0* [TE*]: Transaction Error signal. Warns of errors that are fatal to the transaction as a whole. ST1* [BS*]: Busy signal. Asserted by the slave. ST1* [ED*]: End of Data signal. Carried during the data and disconnection phase. ST2* [SL*]: SeLected signal. Asserted by the slave indicating that the selected resource resides on it's card. ST3* [BC*]: Local Broadcast signal. Asserted by the Slave to indicate that this is a transaction to a broadcast resource. ST4* [TF*]: Transaction Flag. ST5* [IV*]: InterVention signal. Used in a cache coherent environment. Used by other modules to supply updated data. ST6* [BE*]: Beat Error signal. Asserted is a parity error occurs in the connection or data phase. ST7* [WT*]: WaiT signal. Driven by the slave to indicate it is unable to respond to the requested transaction. TG[7 .. 0]*: Tag lines. (undefined) TP*: Tag Parity line. Parity signal for the Tag lines. TP* is asserted when the number of bits in TG is even. Extracted from DS3805 Futurebus+ Protocol Controller, Data Sheet; National Semiconductor @1992