PXI Express Peripheral Bus Connector Pinout and Signal Names
The PXI Express Peripheral slot pinout is provided below.
| Pin # | Signal Name | Signal Name | Signal Name | Signal Name | Signal Name | 4">Signal Name | Signal Name |
| -- | Row Z | Row A | Row B | Row C | Row D | Row E | Row F |
| 1 | GND | GA4 | GA3 | GA2 | GA1 | GA0 | GND |
| 2 | GND | 5Vaux | GND | SYSEN# | WAKE# | ALERT# | GND |
| 3 | GND | 12V | 12V | GND | GND | GND | GND |
| 4 | GND | GND | GND | 3.3V | 3.3V | 3.3V | GND |
| 5 | GND | PXI_TRIG3 | PXI_TRIG4 | PXI_TRIG5 | GND | PXI_TRIG6 | GND |
| 6 | GND | PXI_TRIG2 | GND | ATNLED | PXI_STAR | PXI_CLK10 | GND |
| 7 | GND | PXI_TRIG1 | PXI_TRIG0 | ATNSW# | GND | PXI_TRIG7 | GND |
| 8 | GND | RSV | GND | RSV | PXI_LBLL6 | PXI_LBR6 | GND |
| Pin # | Signal Name | Signal Name | Signal Name | Signal Name | Signal Name | Signal Name | Signal Name | Signal Name | Signal Name |
| -- | Row A | Row B | Row ab | Row C | Row D | Row cd | Row E | Row F | Row ef |
| 1 | PXIe_CLK100+ | PXIe_CLK100- | GND | PXIe_SYNC100+ | PXIe_SYNC100- | GND | PXIe_DSTARC+ | PXIe_DSTARC- | GND |
| 2 | PRSNT# | PWREN# | GND | PXIe_DSTARB+ | PXIe_DSTARB- | GND | PXIe_DSTARA+ | PXIe_DSTARA- | GND |
| 3 | SMBDAT | SMBCLK | GND | RSV | RSV | GND | RSV | RSV | GND |
| 4 | MPWRGD | PERST# | GND | RSV | RSV | GND | 1Refclk+ | 1Refclk- | GND |
| 5 | 1PETp0 | 1PETn0 | GND | 1PERp0 | 1PERn0 | GND | 1PETp1 | 1PETn1 | GND |
| 6 | 1PETp2 | 1PETn2 | GND | 1PERp2 | 1PERn2 | GND | 1PERp1 | 1PERn1 | GND |
| 7 | 1PETp3 | 1PETn3 | GND | 1PERp3 | 1PERn3 | GND | 1PETp4 | 1PETn4 | GND |
| 8 | 1PETp5 | 1PETn5 | GND | 1PERp5 | 1PERn5 | GND | 1PERp4 | 1PERn4 | GND |
| 9 | 1PETp6 | 1PETn6 | GND | 1PERp6 | 1PERn6 | GND | 1PETp7 | 1PETn7 | GND |
| 10 | RSV | RSV | GND | RSV | RSV | GND | 1PERp7 | 1PERn7 | GND |
Additional PXI notes:
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PXI stands for Compact PCI for Instrumentation Bus The pin descriptions which indicate a Key is not a pin, but a male or female void [key]. The V(I/O) pins are un-named in this table. In a +5 volt system the V(I/O) pins are +5volts, in a +3.3volt system the V(I/O) pins are +3.3 volts. PXI [and cPCI] uses 2mm 'Hard Metric'; IEC 1076-4-101, a number of different pin arrangements. Normally the outside Ground rows (which are compression pins) 'Z' and 'F' are not counted as pins. OEM pin numbering may be by cPCI or in accordance with IEC 61076-4-101 (which is reversed). The term "Hard Metric" only means that metric dimensions are preferred ~ with-out regard to inches. PXI [and cPCI] 2mm connectors mating distances [12.50mm] matches the 96 pin DIN 41612 connectors used with other EuroCard packaging [IEC 273 or IEEE 1101, 1101.10], like VMEbus. FutureBus connectors, which also use 2mm style has a mating distance of 10mm, and is not compatible with cPCI connectors. |
Back to the main PXIe Compact PCI [cPCIe] for Instrumentation Bus page, which contain a description of the bus, connector manufacturer, and IC manufacturer links.
Design Key words: PXIe, Instrumentation, CompactPCI, Compact Peripheral Component Interface, cPCI, cPCI Pinouts, P1/J1 Pinouts, Pin Outs, 2mm Connector, Signal Names, 5row, Description Embedded Parallel Computer Bus, Signals, Pin Number, Assignment, Specification, Standard, Defined, Constraint, Properties, Lines, Data, Labels
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